Title :
Noc Architecture Study with DFG Model
Author :
Jia, Liu ; Zheying, Li ; Shuo, Li
Author_Institution :
Inst. of Micro Electron. Applic. Technol., Beijing Union Univ., Beijing, China
Abstract :
Generic reconfigurable network on chip (GRNoC) is an advanced technology of application specified SoC design for digital signal process system (DSPS). A novel GRNoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model combined with graph model of GRNoC, therefore, can be the base of route mapping design for the GRNoC. In addition, node architecture of simple router used in GRNoC is also proposed in this paper. The simple router can increases the properties of data transmission in GRNoC and is more suitable for mapping design with DFG model.
Keywords :
data flow graphs; digital signal processing chips; network routing; network-on-chip; synchronisation; DSPS; NoC architecture; application specified SoC design; central memory; data flow graph; data transmission properties; data transmission speed; digital signal process system; generic reconfigurable network-on-chip; heterogeneous processors; intellectual properties; node architecture; route mapping design; synchronization; Computer architecture; Data communication; Data models; Digital signal processing; IP networks; Program processors; Tiles; DFG; NoC; SoC;
Conference_Titel :
Pervasive Computing Signal Processing and Applications (PCSPA), 2010 First International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4244-8043-2
Electronic_ISBN :
978-0-7695-4180-8
DOI :
10.1109/PCSPA.2010.223
