DocumentCode
3087575
Title
A pattern compaction technique for power estimation based on power sensitivity information
Author
Hsu, ChihYuiig ; Chaur-Wen Wei ; Shen, WenZen
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
5
fYear
2001
fDate
2001
Firstpage
467
Abstract
We propose an efficient power estimation technique for CMOS combinational circuits based on power sensitivity information of primary inputs. We compacted a large sequence of input patterns into a much smaller ones, which also preserved the statistical properties of the original sequence. The experimental results showed our compaction method achieved high compaction ratio within reasonable loss in the accuracy for average power estimation
Keywords
CMOS logic circuits; circuit simulation; combinational circuits; graph theory; logic simulation; low-power electronics; CMOS combinational circuits; average power estimation; compaction method; input patterns; loss; pattern compaction technique; power sensitivity information; primary inputs; statistical properties; CMOS technology; Circuit simulation; Combinational circuits; Compaction; Computational modeling; Energy consumption; Hamming distance; Power engineering and energy; Power system simulation; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922086
Filename
922086
Link To Document