Full chip ESD design rule checking

Electrostatic discharge (ESD) protection is essential for reliability and high yield. ESD design rule checking, however, is beyond the scope of commercial DRC tools. We have presented previously an ESD design rule checker for individual I/O cells. Full chip ESD design rules come in a myriad number of ways and are heavily process dependent. To check them one by one requires rewriting the design rule checker program for each process generation. This paper presents a framework for full chip ESD design rule checking adaptive to how full chip ESD design rules are derived