DocumentCode
3087810
Title
A new self-aligned quantum-well MOSFET architecture fabricated by a scalable tight-pitch process
Author
Jianqiang Lin ; Xin Zhao ; Tao Yu ; Antoniadis, Dimitri A. ; del Alamo, Jesus A.
Author_Institution
Microsyst. Technol. Labs., MIT, Cambridge, MA, USA
fYear
2013
fDate
9-11 Dec. 2013
Abstract
We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features a scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables the precise design of the length and thickness of the ledge and allows the careful balancing of performance against short-channel effects. We demonstrate Lg=70 nm InAs MOSFETs with a ledge length of 5 nm that feature a record gm of 2.7 mS/μm. Separately, devices with a ledge length of 70 nm yield a record ON-current of 410 μA/μm (Vdd=0.5 V and Ioff=100 nA/μm). We also demonstrate working MOSFETs with Lg = 20 nm and a very tight metal contact spacing. Devices with a 5 nm ledge length reveal for the first time the existence of off-state leakage (GIDL) in III-V MOSFETs.
Keywords
III-V semiconductors; MOSFET; etching; indium compounds; quantum well devices; GIDL; III-V MOSFET; InAs; InAs MOSFET; QW-MOSFET; channel access region; digital etching; self-aligned quantum-well MOSFET; size 20 nm; size 5 nm; tight-pitch process; HEMTs; Indium gallium arsenide; Indium phosphide; Logic gates; MOSFET; Resistance; Surface treatment;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/IEDM.2013.6724640
Filename
6724640
Link To Document