Title :
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint
Author :
Chiu, Po-Xun ; Lin, Yu-Chung ; Hsieh, Yi-Ling ; Hsieh, Tsai-Ming
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Abstract :
In this paper, we propose a low power driven re-synthesis algorithm for LUT-based heterogeneous FPGA under delay constraint. We start with a delay optimal solution by using HeteroMap. The solution is then processed to reduce the power consumption and the circuit delay is held. Experimental results show that power consumption of the original mapping solution has been reduced by 15.02%. In addition, our algorithm can further reduce the power consumption when the delay constraint is relaxed
Keywords :
circuit CAD; delays; field programmable gate arrays; high level synthesis; integrated circuit design; low-power electronics; table lookup; HeteroMap; LUT-based FPGA; delay constraint; delay optimal solution; heterogeneous FPGA; low power driven re-synthesis algorithm; power consumption reduction; Capacitance; Delay; Energy consumption; Field programmable gate arrays; Flexible printed circuits; Power engineering and energy; Power engineering computing; Programmable logic arrays; Table lookup; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922099
