DocumentCode :
3087849
Title :
High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator tri-gate MOSFETs with high short channel effect immunity and Vth tunability
Author :
SangHyeon Kim ; Yokoyama, Masafumi ; Nakane, Ryosho ; Ichikawa, Osamu ; Osada, Takenori ; Hata, Masaharu ; Takenaka, Mitsuru ; Takagi, Shinichi
Author_Institution :
Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
fYear :
2013
fDate :
9-11 Dec. 2013
Abstract :
We have investigated the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that body thickness (Tbody) scaling provides better SCEs control, whereas Tbody scaling causes the reduction of the mobility limited by channel thickness fluctuation (δTbody) scattering (μfluctuation). To achieve better SCEs control, the thickness of channel layer (Tchannel) scaling is more favorable than the thickness of MOS interface buffer layer (Tbuffer) scaling, indicating necessity of quantum well (QW) channel structure. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/um. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control.
Keywords :
III-V semiconductors; MOS integrated circuits; MOSFET; electrostatics; scaling circuits; semiconductor quantum wells; InAs; InAs-on-insulator; MOS interface buffer layer; bias voltage control; channel layer; channel length; channel thickness fluctuation; electrical properties; electrostatic; extremely thin body; quantum well; short channel effect immunity; size 20 nm; tri-gate MOSFET; tri-gate structure; vertical scaling; Fabrication; Fluctuations; Indium gallium arsenide; Logic gates; MOSFET; Performance evaluation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
Type :
conf
DOI :
10.1109/IEDM.2013.6724642
Filename :
6724642
Link To Document :
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