Synthesis of partition-codec architecture for low power and small area circuit design

Partitioning circuits for low power design at the logic level has been proposed as a very effective technique. However, the increased area of latches for duplicated input of multiple partitions always offsets the advantage. In this paper we propose a novel Partition-Codec Architecture to achieve low power and small area. The approach is based on evenly partition the output vectors by the corresponding input variables and re-assigning the output vectors of each partition to minimize the number of input vectors and Hamming distance of each partition, and one of the active decoders returns the value to its original output. Given a combinational circuit described by PLA, we develop a global-encoding algorithm, which consists of partition and re-assigning routines to synthesize the Parition-Codec Architecture to achieve low power and small area. Experimental results show that up to 69.5% power reduction, as well as 60.9% area decreased and average 35.7% power saving with 58.4% area reduction are achievable