Title :
50-GHz interconnect design in standard silicon technology
Author :
Kleveland, B. ; Lee, T.H. ; Wong, S.S.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Coplanar waveguides were fabricated in a process that emulates silicon CMOS technologies with 5 to 10 metal layers. The observed S/sub 21/ loss of 0.3 dB/mm at 50 GHz is among the lowest ever reported with standard Al interconnects on Si/SiO/sub 2/. Optimum design parameters were counter-intuitive: in some frequency ranges, the lowest loss was achieved with relatively narrow lines over a low-resistivity substrate. This was exploited in the design of transmission lines that are fully compatible with a CMOS technology. The process emulation was calibrated with a commercial 4-layer Al/Cu CMOS technology.
Keywords :
CMOS integrated circuits; coplanar waveguides; field effect MIMIC; integrated circuit interconnections; 50 GHz; Al-Cu; Si-SiO/sub 2/; coplanar waveguide; interconnect design; loss; process emulation; silicon CMOS technology; transmission line; CMOS process; CMOS technology; Conductivity; Coplanar waveguides; Dielectric substrates; Frequency; Impedance; Integrated circuit interconnections; Scattering parameters; Silicon;
Conference_Titel :
Microwave Symposium Digest, 1998 IEEE MTT-S International
Conference_Location :
Baltimore, MD, USA
Print_ISBN :
0-7803-4471-5
DOI :
10.1109/MWSYM.1998.700873
