Title :
Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers
Author :
Duriez, Blandine ; Vellianitis, G. ; van Dal, M.J.H. ; Doornbos, G. ; Oxland, Richard ; Bhuwalka, Krishna K. ; Holland, Martin ; Chang, Y.S. ; Hsieh, C.H. ; Yin, K.M. ; See, Y.C. ; Passlack, Matthias ; Diaz, Carlos H.
Author_Institution :
TSMC, Leuven, Belgium
Abstract :
We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak gm, ext=2.7mS/μm (gm, int=3.3mS/μm), Q (≡gm, ext/SSsat) = 32.4 and Ion= 497μA/μm at Ioff = 100nA/μm, all at Vds= -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low Dit gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (gm/SS metric) and ~2× (Ion/Ioff metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.
Keywords :
MOSFET; elemental semiconductors; germanium; semiconductor device manufacture; semiconductor device models; silicon; Ge; Si; Si wafers; gate high-k/metal gate; p-channel FinFET; size 20 nm; size 300 mm; voltage -0.5 V; Capacitance; FinFETs; Logic gates; Measurement; Silicon;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724666