Title :
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
Author :
Bangsaruntip, Sarunya ; Balakrishnan, K. ; Cheng, S.-L. ; Chang, Joana ; Brink, M. ; Lauer, I. ; Bruce, Robert L. ; Engelmann, Sebastian U. ; Pyzyna, A. ; Cohen, Guy M. ; Gignac, Lynne ; Breslin, Chris M. ; Newbury, J.S. ; Klaus, D.P. ; Majumdar, Angshul
Author_Institution :
Res. Div., T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
Abstract :
We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.
Keywords :
CMOS integrated circuits; MOSFET; elemental semiconductors; field effect transistors; nanowires; semiconductor device manufacture; silicon; CMOS; NFET; Si; density scaling; gate-all-around silicon nanowire MOSFET; size 10 nm; size 30 nm; size 60 nm; Annealing; CMOS integrated circuits; Epitaxial growth; Logic gates; Nanoscale devices; Performance evaluation; Silicon;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724667
