Title :
A practical algorithm for retiming level-clocked circuits
Author :
Maheshwari, Naresh ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
A new approach for fast retiming of level-clocked circuits is presented. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retiming solution is computationally cheap. The minimum period retiming for each of the ISCAS89 circuits was obtained within minutes by this algorithm
Keywords :
VLSI; circuit optimisation; clocks; flip-flops; logic CAD; timing; CAD; ISCAS89 circuits; clock retiming; clock skew; clock skew optimization; gates; latches; level-clocked circuit retiming; minimum period retiming; optimal skew solution; problem size; Circuits; Clocks; Constraint theory; Delay effects; Equations; Latches; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563591
