Title :
3D heterogeneous integration for analog
Author :
Samoilov, Arkadii V. ; Tran, Khoi-Nguyen ; Kerness, Nicole ; Jones, John ; McNally, Peter ; Barnett, Stanley ; Parent, Tyler ; Ellul, Joseph ; Srivastava, Anurag ; Ikeuchi, Katsushi ; Tie Wang ; Tiao Zhou
Author_Institution :
Maxim Integrated, San Jose, CA, USA
Abstract :
We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate the highest reported capacitor density of C=1 μF/mm2 (=1,000 fF/μm2) and the figure of merit (FOM) C*Vbd=11 C/m2 (Vbd is the breakdown voltage). Through-Si vias can be used to combine passive and active die into a single stack. Addition of optical layers to the Bipolar CMOS DMOS (BCD) process allows light detection in the visible and infrared range. 3D package-level integration is illustrated by embedding of multiple active and passive components in one package.
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; elemental semiconductors; integrated circuit packaging; silicon; three-dimensional integrated circuits; 3D package-level integration; Si; active components; active die; bipolar CMOS DMOS; breakdown voltage; figure of merit; integrated capacitors; light detection; optical sensors; packaging technologies; passive components; passive die; through-Si vias; wafer-level 3D integration; wafer-level technologies; Capacitance; Capacitors; MIM capacitors; Optical filters; Optical sensors; Substrates; Three-dimensional displays;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724688
