A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

Author

Nishii, O. ; Arakawa, F. ; Ishibashi, K. ; Nakano, S. ; Shimura, T. ; Suzuki, K. ; Tachibana, M. ; Totsuka, Y. ; Tsunoda, T. ; Uchiyama, K. ; Yamada, T. ; Hattori, T. ; Maejima, H. ; Nakagawa, N. ; Narita, S. ; Seki, M. ; Shimazaki, Y. ; Satomura, R. ; Ta

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

288

Lastpage

289

Abstract

This 200 MHz CMOS 2-issue superscalar microprocessor is redesigned with a 0.25 /spl mu/m 5-metal-layers CMOS process (L/sub eff/=0.20 /spl mu/m). In this chip 3.2M transistors are implemented in a 7.6/spl times/7.6 mm/sup 2/ die. This chip for low-cost graphic, embedded applications achieves 1.4 GFLOPS at 200 MHz with low-power consumption. This chip integrates CPU, FPU, 8 kB direct-mapped instruction cache (IC), 16 kB direct-mapped data cache (DC), MMU (64-entry unified TLB and 4-entry ITLB), bus interface logic, and six peripherals which are DMAC, timer unit (TMU), real time clock (RTC), serial comm. interface (SCI), interrupt controller (INTC), and emulation/debug unit (EMU). The bus interface provides glueless connections to SRAM, DRAM, SDRAM, burst-ROM, and PCMCIA, bus operation includes 8-, 16-, 32-, and 64b bus widths.

Keywords

CMOS digital integrated circuits; 0.25 micron; 1.2 W; 1.4 GFLOPS; 200 MHz; CMOS superscalar microprocessor; embedded graphic operation unit; low-power circuit; CMOS integrated circuits; CMOS process; Central Processing Unit; Clocks; Frequency; Graphics; Laboratories; Logic; Microcomputers; Microprocessors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672469

Filename

672469