DocumentCode :
3088875
Title :
Design optimization of wiring substrate in a CMOS-based multichip module
Author :
Sudo, Toshio ; Hirano, Naohiko ; Kato, Katsuto ; Hiruta, Youichi ; Fuchida, Yumi
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fYear :
1992
fDate :
18-20 May 1992
Firstpage :
710
Lastpage :
716
Abstract :
The effects of line resistance on the electrical performance in CMOS-based MCMs are described. Switching noise, ringing noise, interconnect delay, and crosstalk noise in the line resistance range of a thin-film wiring substrate are discussed. Signal line resistance works as a damping resistor both for switching noise and for signal ringing noise. There are optimum damping conditions. The chip-to-chip delay was not substantially influenced by the line resistance as long as the line length was kept short. The line resistance, i.e. the characteristic impedance, as well as the line resistance has an important role in determining the signal propagation properties whether it behaves like an RC delay or it is in the region of the time of flight. The design of the wiring substrate must be optimized for CMOS buffer drivability to have good electrical properties and not to impose excessive requirements on thin-film process technology
Keywords :
CMOS integrated circuits; crosstalk; large scale integration; multichip modules; optimisation; substrates; CMOS buffer drivability; CMOS-based multichip module; LSI; RC delay; crosstalk noise; design optimisation; effects of line resistance; electrical performance; interconnect delay; optimum damping conditions; ringing noise; switching noise; wiring substrate; Crosstalk; Damping; Delay; Design optimization; Electric resistance; Impedance; Resistors; Substrates; Transistors; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1992. Proceedings., 42nd
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0167-6
Type :
conf
DOI :
10.1109/ECTC.1992.204282
Filename :
204282
Link To Document :
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