Design of High-Speed DDC Based Multi-stage

Author

Ming, Chen ; Houde, Quan ; Huan, Zhao ; Wei, Liang

Author_Institution

Ordnance Eng. Coll., Shijiazhuang, China

fYear

2010

fDate

17-19 Sept. 2010

Firstpage

936

Lastpage

939

Abstract

This paper presents a multi-stage digital-down-converter (DDC) bases on nπ/4 fixed frequency down-conversion. From the contradiction between high-speed processing and the challenge of FPGAs hardware resources in the typical direct frequency conversion, special design are applied to optimize the mixers and filters for reducing peak processing rate of system. Analysis the frequency remaining in mixing and alias of anti-flod spectrum problem which triggered in multi-stage DDC. The simulation result proves that it supports 240MHz no-alias DDC while low-pass sampling at a low peak processing rate below 120MHz.

Keywords

field programmable gate arrays; frequency convertors; FPGA; antiflod spectrum problem; digital-down-converter; fixed frequency down-conversion; frequency 240 MHz; high-speed DDC based multistage; high-speed processing; low-pass sampling; peak processing rate; Bandwidth; Baseband; Field programmable gate arrays; Low pass filters; Mixers; Table lookup; FPGA; low-pass sample; multi-stage DDC;

fLanguage

English

Publisher

ieee

Conference_Titel

Pervasive Computing Signal Processing and Applications (PCSPA), 2010 First International Conference on

Conference_Location

Harbin

Print_ISBN

978-1-4244-8043-2

Electronic_ISBN

978-0-7695-4180-8

Type

conf

DOI

10.1109/PCSPA.2010.231

Filename

5635923