DocumentCode
3088966
Title
A study on the performance, complexity tradeoffs of block turbo decoder design
Author
Chi, Zhipei ; Song, Leilei ; Parhi, Keshab K.
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
65
Abstract
In this paper, results from a study of the tradeoffs between VLSI implementation complexity and performance of block turbo decoder are presented. Specifically, we address low complexity design strategies on choosing the scaling factor of the log extrinsic information, reducing the number of hard decision decodings and reducing the complexity of general hard-decision BCH decoders when soft-decision decodings are utilized
Keywords
BCH codes; VLSI; block codes; decoding; turbo codes; VLSI implementation complexity; block turbo decoder design; hard-decision BCH decoders; log extrinsic information; low complexity design strategies; performance-complexity tradeoffs; scaling factor; soft-decision decodings; Bit error rate; Block codes; Decoding; Encoding; Error correction codes; Forward error correction; Gain; High speed optical techniques; Turbo codes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922170
Filename
922170
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