A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

Author

Kubosawa, H. ; Takahashi, H. ; Ando, S. ; Asada, Y. ; Asato, A. ; Suga, A. ; Kimura, M. ; Higaki, N. ; Miyake, H. ; Sato, T. ; Anbutsu, H. ; Tsuda, T. ; Yoshimura, T. ; Amano, I. ; Kai, M. ; Mitarai, S.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

290

Lastpage

291

Abstract

A microprocessor with single instruction multiple data stream (SIMD) architecture and as many as 170 media instructions for multimedia embedded systems meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and 3DCG image processing capabilities, (b) programming flexibility, and (c) low power dissipation and low cost. It also works as a general purpose microprocessor with mid-range performance. The microprocessor uses 0.21 /spl mu/m CMOS technology, and the chip achieves 2.16 GOPS/720 MFLOPS at a 180 MHz operation with 1.2 W dissipation.

Keywords

CMOS digital integrated circuits; 0.21 micron; 1.2 W; 180 MHz; 3DCG image processing; 720 MFLOPS; CMOS technology; MPEG2 decoding; SIMD architecture; embedded superscalar microprocessor; multimedia application; Arithmetic; Clocks; Data processing; Decoding; Image processing; Microprocessors; Multimedia systems; Power dissipation; Reduced instruction set computing; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672470

Filename

672470