Title :
A low cost, high quality embedded array DFT technique for high performance processors
Author :
Bao, Zhuoyu ; Kumar, Suriya A. ; Wu, David M. ; Natarajan, Vimal K. ; Lin, Mike
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by ∼50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel® high performance microprocessor design.
Keywords :
built-in self test; microprocessor chips; design for testability; direct access test controller; embedded array DFT technique; high performance processors; manufacturing test time reduction; parallel DAT interface; programmable on-die test generation engine; Clocks; Costs; Design for testability; Electronic equipment testing; Integrated circuit yield; Logic arrays; Logic testing; Manufacturing processes; Microprocessors; Silicon;
Conference_Titel :
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Print_ISBN :
0-7695-2500-8
DOI :
10.1109/DELTA.2006.5
