Challenges in low-k integration of advanced Cu BEOL beyond 14 nm node

Interconnect strategy is considered in the technology trend, including planar to FinFET conversion. More capacitive element of FinFET than the conventional planar FET requires lower resistance for the long interconnect, which can be realized by high aspect ratio (AR) wiring. In order to compensate high capacitance due to high AR in short interconnect range, we still need lower k for ILD. Regarding the low-k technology trend, we have issues of PID (plasma-induced damage) and CPI (chip-package interaction) in integration of k~2.5, delaying introduction of much lower k material. High carbon content and enhancing Si-C-Si bridging bond are keys to improve integration performance.