Author :
Matsuda, Tadamitsu ; Lee, John Jaehwan ; Han, K.H. ; Park, K.H. ; Cha, J.O. ; Baek, J.M. ; Yim, T.J. ; Kim, D.C. ; Lee, D.H. ; Kim, J.N. ; Choi, S.H. ; Lee, E. ; Nam, S.D. ; Lee, H.B. ; Cho, Y.W. ; Kim, Ihn Seok ; Kwon, B.H. ; Ahn, S.H. ; Yun, J.H. ; Kim,
Author_Institution :
Samsung Electron. Co., Ltd., Hwasung, South Korea
Abstract :
It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.
Keywords :
chemical vapour deposition; copper; electric breakdown; integrated circuit metallisation; ruthenium; CVD-Ru liner instead; Cu; Cu metallization; Cu void issues; PVD Ta liner; Ru; Ru integration scheme; Ru liner integration; TDDB performance degradation; gapfill performance; optimized integration scheme; Degradation; Metals; Performance evaluation; Resistance; Robustness; Water;
