Title :
The design of current mode CMOS multiple-valued circuits
Author :
Chang, Young-Hoon ; Butler, Jon T.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Abstract :
A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizations that are almost as good. A cost-table that results in better realizations than obtained with a previous cost-table is proposed
Keywords :
CMOS integrated circuits; many-valued logics; search problems; AND-OR tree; cost-table technique; heuristic search technique; multiple-valued current-mode CMOS logic; vertical partitioning algorithm; Adders; Algorithm design and analysis; CMOS logic circuits; Charge coupled devices; Cost function; Joining processes; Laboratories; Logic circuits; Logic design;
Conference_Titel :
Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on
Conference_Location :
Victoria, BC
Print_ISBN :
0-8186-2145-1
DOI :
10.1109/ISMVL.1991.130718
