Title :
Skew-tolerant high-speed (STHS) domino logic
Author :
Jung, Seong-Ook ; Yoo, Seung-Moon ; Ki-Wook Kim ; Kang, Sung-Mo Steve
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents skew-tolerant high-speed domino logic. Skew-tolerant high-speed domino logic resolves the floating dynamic node problem of high-speed domino logic and alleviates the strict clock timing requirement. Simulation results show that skew-tolerant high-speed domino logic is more robust to noise and timing variation than high-speed domino logic, while achieving better performance
Keywords :
CMOS logic circuits; VLSI; clocks; high-speed integrated circuits; integrated circuit design; integrated circuit noise; timing; IC noise; clock timing requirement; noise; skew-tolerant high-speed domino logic; timing variation; Clocks; Crosstalk; Degradation; Energy consumption; Leakage current; Logic design; Logic gates; MOS devices; Threshold voltage; Timing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922195
