Title :
A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier
Author :
Carlson, D. ; Jain, A. ; Bannon, P. ; Benninghoff, T. ; Bertone, M. ; Blake-Campos, R. ; Bouchard, G. ; Brasili, D. ; Castelino, R. ; Lilly, B. ; Mehta, S. ; Miller, B. ; Mueller, R. ; Nagarajan, M. ; Olesin, A. ; Yalala, V. ; Saito, Y. ; Chen, A. ; Kobay
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
This microprocessor is optimized for the desktop. The chip contains architectural, circuit, and technology enhancements that include a 32 kB, 2-way set associative virtual instruction cache, a 16 kB, dual-read-ported, physical data cache, and advanced branch prediction. Circuit enhancements include a 6.0 ns integer multiplier, a 19.5 ns floating-point divider, and to support low jitter, 50% duty cycle 667 MHz clock, and an on-chip PLL. The 5.7M transistor microprocessor is fabricated in a 2.0 V, 0.28 /spl mu/m CMOS process with 4-layers of metal for interconnect, measures 1.0 cm/sup 2/, and supports a 2.5 V interface.
Keywords :
CMOS digital integrated circuits; 0.28 micron; 2.0 V; 6.0 ns; 64 bit; 667 MHz; CMOS process; PLL; RISC microprocessor; associative virtual instruction cache; branch prediction; clock; desktop; dual-read-ported physical data cache; floating-point divider; integer multiplier; jitter; Clocks; Delay; Design automation; Integrated circuit interconnections; Logic arrays; Microprocessors; Power supplies; Reduced instruction set computing; Solid state circuits; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672472
