Electrical behavior of GOS fault affected domino logic cell

Author

Comte, M. ; Ohtake, S. ; Fujiwara, H. ; Renovell, M.

Author_Institution

Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan

fYear

2006

fDate

17-19 Jan. 2006

Abstract

Gate-oxide shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in domino cells are proposed.

Keywords

Boolean algebra; CMOS logic circuits; integrated circuit reliability; integrated circuit testing; integrated circuit yield; logic arrays; logic testing; Boolean test; GOS detection; GOS fault; clocked operating principle; defect modeling; domino logic cell; electrical analysis; electrical behavior; gate-oxide shorts; integrated circuit production yield; standard full CMOS cells; CMOS logic circuits; Circuit faults; Circuit testing; Clocks; Integrated circuit modeling; Logic gates; Logic testing; MOS devices; MOSFETs; Semiconductor device modeling; Defect modeling; Domino logic; Electrical analysis Boolean test.; Gate-Oxide Short (GOS);

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on

Print_ISBN

0-7695-2500-8

Type

conf

DOI

10.1109/DELTA.2006.42

Filename

1581209