A phase change memory cell with metallic surfactant layer as a resistance drift stabilizer

We demonstrate a novel confined PCM cell structure which utilizes a metallic surfactant layer to stabilize the high (and intermediate) resistance state drift in MLC phase change memory technology. The metallic surfactant layer provides an alternative conductive path to the amorphous region during read operation, which makes the cell characteristics immune to amorphous region instabilities such as time- and temperature-dependent resistance drift and noise. The data here focuses on time-dependent drift mitigation. Analytical modeling and numerical simulations show that this cell design can achieve as much as 4× larger resistance ratio between adjacent levels in a 4-level cell. Experimental results confirm its effectiveness as a resistance drift stabilizer, showing ~6× smaller drift coefficient, resulting in a substantially reduced bit error rate.