Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications

The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reconfigurable multi-processor-cores SoCs. These processing cores within the SoC can be subsequently connected with each other by a communication-centric NoC, thereby reducing data-traffic problems. The (repetitive) multi-processor-cores feature inside these SoCs, the programmable routing via NoC, as well as the repetitive hardware in the cores themselves provides new opportunities for efficient testing at different hierarchical levels. These opportunities, and the inserted DfT, test vectors and coverage can be subsequently applied for enhancing the dependability of SoCs as well as these cores via self-repair. As examples of new opportunities we introduce the feedback loop and KGC concept for enhancing diagnosis and reducing external communication respectively. The self-repair can be done either by rerouting of unused resources or software remapping of correct resources to an application.