Design and simulation of a high performance rail-to-rail CMOS op-amp at ±3V supply

Author

Bhaskaran, Madhu ; Sriram, Sharath ; Stojcevski, Aleksandar ; Zayegh, Aladin

Author_Institution

Sch. of Electr. Eng., Victoria Univ. of Technol., Melbourne, Vic., Australia

fYear

2006

fDate

17-19 Jan. 2006

Abstract

The paper discusses a CMOS operational amplifier at ± 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V/μs, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.

Keywords

CMOS analogue integrated circuits; circuit simulation; integrated circuit design; operational amplifiers; 25.44 mW; CMOS operational amplifier; bias current reduction; high performance op-amp; rail-to-rail op-amp; Bipolar transistor circuits; Current supplies; Differential amplifiers; Energy consumption; Mirrors; Operational amplifiers; Rail to rail inputs; Rail to rail operation; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on

Print_ISBN

0-7695-2500-8

Type

conf

DOI

10.1109/DELTA.2006.30

Filename

1581216