A neural network model for circuit partitioning in floorplan design

A floorplan design approach that combines both a neural network model for graph bipartitioning procedure and a slicing tree representation in the physical design of VLSI systems is reported in this paper. The circuit to be floorplanned contains a set of functional modules each having a number of possible dimensions and a net-list containing the connectivity information. The slicing tree representation provides an efficient tree traversal operations using recursion for obtaining area-efficient floorplans. The slicing method also eliminates the cyclical conflicts in module placement and hence ensures better routability