A low power carry select adder with reduced area

A carry-select adder can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders. This paper proposes a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For bit length n=64, this new carry-select adder requires 38 percent fewer transistors than the dual ripple-carry carry-select adder and 29 percent fewer transistors than Chang´s carry-select adder using single ripple carry adder. This new 64b adder has 3.45 ns delay time at 2.5 V power supply using a 0.25 um CMOS technology