An FPGA Implementation of the Searcher Algorithm

In wideband code division multiple access (WCDMA) systems rake reception is used to combine signal energies of the different multipath components to form a composite signal with better characteristics. A component that is critical to the proper operation of rake receivers is the path searcher. The searcher estimates the delays of the multipath component where each delay corresponds to a separate multipath component. In this paper we present an FPGA implementation of the path searcher. Details of the implementation and experimental results are discussed. FPGA computational output is verified using MATLAB based simulation.