An FPGA Implementation of the Searcher Algorithm

Author

Sagahyroon, A. ; Tarhuni, M. El ; Ibrahim, S.

Author_Institution

American Univ. of Sharjah, Sharjah

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

85

Lastpage

88

Abstract

In wideband code division multiple access (WCDMA) systems rake reception is used to combine signal energies of the different multipath components to form a composite signal with better characteristics. A component that is critical to the proper operation of rake receivers is the path searcher. The searcher estimates the delays of the multipath component where each delay corresponds to a separate multipath component. In this paper we present an FPGA implementation of the path searcher. Details of the implementation and experimental results are discussed. FPGA computational output is verified using MATLAB based simulation.

Keywords

code division multiple access; field programmable gate arrays; mathematics computing; multipath channels; radio receivers; radio reception; FPGA implementation; MATLAB based simulation; WCDMA system; multipath components; rake receivers; rake reception; searcher algorithm; wideband code division multiple access systems; Algorithm design and analysis; Delay estimation; Electronic equipment testing; Fading; Field programmable gate arrays; MATLAB; Multiaccess communication; Multipath channels; Signal design; Signal generators; FPGA; Searcher; WCDMA;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.83

Filename

4459515