DocumentCode
3090034
Title
Simulation based transistor-SRAM co-design in the presence of statistical variability and reliability
Author
Asenov, Asen ; Cheng, Binjie ; Wang, Xiongfei ; Brown, A.R. ; Reid, Dave ; Millar, C. ; Alexander, C.
Author_Institution
Gold Stand. Simulations Ltd., Glasgow, UK
fYear
2013
fDate
9-11 Dec. 2013
Abstract
We report on a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modelling strategy is developed for early delivery of a reliable PDK with built-in statistical variability and reliability information. This enables TCAD-based transistor-SRAM co-design and path finding for emerging technology nodes.
Keywords
MOSFET; SRAM chips; semiconductor device reliability; silicon-on-insulator; technology CAD (electronics); SOI FinFET transistors; SRAM cell design; Si; TCAD-based transistor; built-in statistical variability; path finding; process impact; reliability; size 14 nm; statistical compact; transistor-SRAM co-design; Correlation; FinFETs; Geometry; Integrated circuit modeling; Performance evaluation; SRAM cells;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/IEDM.2013.6724741
Filename
6724741
Link To Document