Adaptive Diagnostic Pattern Generation for Scan Chains

Author

Wang, Fei ; Hu, Yu ; Li, Xiaowei

Author_Institution

Chinese Acad. of Sci., Beijing

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

129

Lastpage

132

Abstract

Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS´89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.

Keywords

automatic test pattern generation; computability; design for testability; fault diagnosis; integrated circuit testing; logic testing; SAT-based technique; adaptive diagnostic pattern generation; design-for-testability technique; fault diagnosis; logic testing; scan chains; stuck-at faults; Application software; Automatic test pattern generation; Circuit faults; Circuit testing; Electronic equipment testing; Failure analysis; Frequency; Signal resolution; System testing; Test pattern generators; Boolean satisfiability; diagnosis; scan chain; testing; very large scale integration (VLSI);

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.45

Filename

4459525