Title :
Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations
Author :
Avci, Uygar E. ; Morris, Daniel H. ; Hasan, Souleiman ; Kotlyar, Roza ; Raseong Kim ; Rios, Rafael ; Nikonov, Dmitri E. ; Young, Ian A.
Author_Institution :
Components Res., Technol. & Manuf. Group, Intel Corp., Hillsboro, OR, USA
Abstract :
Reducing supply voltage (Vdd) while keeping leakage current low is critical for minimizing energy consumption and improving mobile device battery life. The thermal limit of MOSFET subthreshold slope (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low Vdd. A Tunneling Field Effect Transistor (TFET) is not limited by this thermal tail and may perform better at low Vdd [1,2]. In this paper, a leading N-TFET option - GaSb/InAs heterojunction - is atomistically modeled [3,4] and circuit simulation models are developed to predict 64% average energy savings against Si CMOS at Lg=13nm for a nanowire. Energy savings diminish to 21% without a good P-TFET option. Both MOSFET and TFET device variations are dominated by work-function variation, and TFET energy savings are slightly reduced when variations are considered.
Keywords :
CMOS integrated circuits; MOSFET; circuit simulation; elemental semiconductors; energy conservation; energy consumption; field effect transistors; gallium compounds; indium compounds; leakage currents; nanowires; silicon; CMOS; GaSb-InAs; MOSFET; N-TFET; P-TFET; Si; circuit simulation; energy consumption; energy efficiency; leakage current; mobile device battery life; nanowire; size 13 nm; subthreshold slope; threshold voltage; tunneling field effect transistor; CMOS integrated circuits; Capacitance; Delays; MOSFET; Performance evaluation; Silicon;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724744
