A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

Author

Runsheng Wang ; Mulong Luo ; Shaofeng Guo ; Ru Huang ; Changze Liu ; Jibin Zou ; Jianping Wang ; Jingang Wu ; Nuo Xu ; Waisum Wong ; Yu, Son-Cheol ; Hanming Wu ; Shiuh-Wuu Lee ; Yangyuan Wang

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2013

fDate

9-11 Dec. 2013

Abstract

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

Keywords

CMOS digital integrated circuits; SRAM chips; electron traps; electronic design automation; integrated circuit design; nanotechnology; oscillators; AC effects; MOSFET; RO; SRAM; future nanoCMOS technology; gate oxide traps; industry-standard EDA tools; manufacturing process variations; nanoscale CMOS technology; practical trap-aware device-circuit codesign; realistic digital circuit operations; transient effects; unified approach; CMOS integrated circuits; Degradation; Digital circuits; Integrated circuit modeling; Jitter; Random access memory; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2013 IEEE International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/IEDM.2013.6724745

Filename

6724745