Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC

In the present and future multimedia applications it becomes necessary to integrate the influence of external and internal parameters such as bit rate, bandwidth, energy and available computation resources. The target system implementing such application must also take in account the variation of these parameters according to its environment. The modern FPGAs offer partial and dynamic reconfiguration possibilities in terms of computation elements. Moreover, these FPGAs integrate diverse clock regions and frequency variation possibilities allowing thus multi-clock and multi-frequency operations. In this paper we exploit the association of slowdown technique by using dynamic variation of clock frequency and variable performance using partial and dynamic reconfiguration to enhance the global auto-adaptability of system on programmable chip in terms of energy, efficiency and scalability. The architectural support for auto-adaptive system is described and first results for JPEG2000 application targeting virtex-4 FPGA are discussed.