DocumentCode :
3090183
Title :
Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression
Author :
Zhang, Milin ; Bermak, Amine
Author_Institution :
Hong Kong Univ. of Sci. & Technol., Hong Kong
fYear :
2008
fDate :
23-25 Jan. 2008
Firstpage :
167
Lastpage :
170
Abstract :
In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30 dB with a compression ratio of less than 3 BPP.
Keywords :
VLSI; sensor arrays; block divided storage; image capture; image storage; low storage digital pixel sensor array; on-line block-based compression; Biosensors; Compression algorithms; Counting circuits; Image coding; Image storage; Pulse width modulation; Sensor arrays; Space vector pulse width modulation; Time domain analysis; Voltage; DPS; block-based compression; error propagation; low storage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3110-6
Type :
conf
DOI :
10.1109/DELTA.2008.117
Filename :
4459533
Link To Document :
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