DocumentCode
3090318
Title
Yield estimates for the TESH multicomputer network
Author
Maziarz, B.M. ; Jain, V.K.
Author_Institution
Univ. of South Florida, Tampa, FL, USA
fYear
2002
fDate
2002
Firstpage
20
Lastpage
28
Abstract
Reconfiguration and yield issues are considered for parallel computing systems based on a new interconnection network, "Tori connected mESHes (TESH)." The network is hierarchical - thus allowing exploitation of computation locality as well as systematic expansion up to a million processors, permits efficient VLSI/ULSI realization, and appears to be well suited for 3-D VLSI/ULSI implementation. Further, it enables efficient implementation of a large variety of computation intensive applications. In a very recent paper, we have reported the methodology for automatic reconfiguration of TESH. The goal of the present paper is to derive theoretical estimates of system yield as a function of the defect density and the various reconfiguration approaches. From these bounds, it is concluded that despite dramatic improvements in defect density in recent years, it is still necessary to provide redundancy and defect circumvention to achieve acceptable system-level yields. The analysis includes consideration of not only cell yield, but also switch and link yields. The latter two are particularly important in view of the emerging interest in interconnected nanotech devices for which the link yields currently are quite low.
Keywords
ULSI; VLSI; fault tolerant computing; multiprocessor interconnection networks; nanotechnology; reconfigurable architectures; redundancy; TESH multicomputer network; ULSI; VLSI; automatic reconfiguration; cell yield; computation locality; defect circumvention; defect density; hierarchical network; interconnected nanotech devices; interconnection network; link yields; redundancy; switch yields; system yield; systematic expansion; tori connected meshes; yield issues; Computer applications; Computer networks; Estimation theory; Multiprocessor interconnection networks; Nanoscale devices; Parallel processing; Switches; Ultra large scale integration; Very large scale integration; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-1831-1
Type
conf
DOI
10.1109/DFTVS.2002.1173498
Filename
1173498
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