A simplified gate-level fault model for crosstalk effects analysis

The relevant problem of crosstalk affects the design process in many ways. Its delay effects can not be easily addressed due to the complex interaction between signals and dependency on the logical, functional and timing aspects of the design. In this paper we propose a modelling approach and a methodology to assess crosstalk effects on real designs through a simulation-based analysis environment. Results are reported showing how the proposed approach has been used to validate the bus architecture inside the LEON SPARC-like processor core.