A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier

Author

Tanabe, A. ; Soda, M. ; Nakahara, Y. ; Furukawa, A. ; Tamura, T. ; Yoshida, K.

Author_Institution

Ultra-LSI Res. Lab., Japan

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

304

Lastpage

305

Abstract

A single chip 2.4 Gb/s optical receiver IC for the next generation access system integrates a preamplifier, automatic offset and gain controller (AGC), phase-locked loop (PLL) and 1:8 demultiplexer (DEMUX) using a 0.15 /spl mu/m bulk CMOS process, realizing low cost and low power consumption. The preamplifier reduces the effect of noise caused by substrate crosstalk and has 5.9 GHz bandwidth and 59 dB/spl Omega/ transimpedance gain. Input current from the photodiode is transformed into a voltage by the preamplifier and then amplified by the AGC circuit. The PLL circuit extracts the clock from input data and the DEMUX circuit converts input serial data into 8 b parallel data.

Keywords

CMOS integrated circuits; 0.15 micron; 2.4 Gbit/s; 5.9 GHz; AGC circuit; CMOS optical receiver IC; PLL; automatic gain controller; automatic offset controller; bulk CMOS process; clock extraction; demultiplexer; low cost design; low power consumption; low substrate crosstalk preamplifier; phase-locked loop; photodiode detector; single chip optical receiver; Automatic generation control; CMOS integrated circuits; CMOS process; Control systems; Crosstalk; Optical control; Optical receivers; Phase locked loops; Photonic integrated circuits; Preamplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672476

Filename

672476