Title :
Evaluation time estimation for pass transistor logic circuits
Author :
Prasad, P.W.C. ; Mills, B.I. ; Assi, A. ; Raseen, M. ; Senanayake, S.M.N.A. ; Prasad, V.C.
Author_Institution :
Coll. of Inf. Technol., UAE Univ.
Abstract :
This paper describes a mathematical model for the prediction of binary decision diagram (BDD) depth measures, such as the longest path length (LPL) and the average path length (APL). The formal core of the model is a formula for the average LPL and APL over the set of BDD derived from Boolean logic expressions with a given number of variables and product terms. The formula was determined by extensive empirical studies of these measures. The proposed model can provide valuable information about Pass Transistor Logic (PTL) evaluation time for any variable ordering method without building the BDD. Our experimental results show good correlation between the theoretical results and those predicted by the mathematical model, which will greatly reduce the time complexity of applications that use BDDs
Keywords :
Boolean algebra; binary decision diagrams; logic circuits; network analysis; transistor circuits; Boolean logic expressions; binary decision diagram; depth measures; evaluation time estimation; mathematical model; pass transistor logic circuits; Binary decision diagrams; Boolean functions; Data structures; Delay; Educational institutions; Equations; Information technology; Logic circuits; Logic functions; Mathematical model;
Conference_Titel :
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7695-2500-8
DOI :
10.1109/DELTA.2006.47
