A low-complexity and high-speed Booth-algorithm FIR architecture

A low-complexity and high-speed transposed direct-form finite-impulse-response (FIR) architecture is developed based on the radix-4 Booth algorithm. It includes a pre-processing unit, input sub-data latches, a control unit, Booth decoders, filter coefficient registers, an accumulation path and a post-processing unit. To decrease hardware complexity, the pre-processing unit, input sub-data latches and Booth decoders are explored by using the 2-bit word length of sub-data latches instead of the conventional 3-bit one. In addition, the accumulation path using the carry save adders is designed by using the addition delay scheme to minimize the numbers of half adders and latches as compared to the conventional Booth-algorithm FIR architecture. The proposed FIR architecture can reduce more hardware complexities as the word length of input data, and the tap number of FIR increase. For example, when the 8-tap FIR with 8-bit input data, and the 256-tap FIR with 16-bit input data are designed, the proposed FIR architecture would save about 11% and 25% of hardware complexity respectively