Title :
Partially duplicated code-disjoint carry-skip adder
Author :
Marienfeld, D. ; Ocheretnij, V. ; Gössel, M. ; Sogomonyan, E.S.
Author_Institution :
Dept. of Comput. Sci., Univ. of Potsdam, Germany
Abstract :
In this paper a new self-checking code-disjoint partially duplicated fast carry-skip adder is proposed which is for 64 bits the fastest self-checking adder known so far. For the first time the adder cells of a fast carry-ripple adder are used for the design of a carry-skip adder. The propagate signals are implemented only once. They are utilized to compute the duplicated sum bits and simultaneously to check the input parity and some internal XOR-gates.
Keywords :
adders; carry logic; logic gates; parity check codes; 64 bit; adder cells; carry-skip adder; code-disjoint adder; duplicated sum bits; input parity; internal XOR-gates; partially duplicated circuits; propagate signals; self-checking adder; Adders; Circuit faults; Clocks; Computer errors; Computer science; Electrical fault detection; Fault detection; Fault tolerance; Propagation delay; Signal generators;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
Print_ISBN :
0-7695-1831-1
DOI :
10.1109/DFTVS.2002.1173504
