A Jittered-Sampling Correction Technique for ADCs

Jittered sampling raises the noise floor in Analogue to Digital Converters (ADCs). This leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This extended abstract proposes a technique that compensate for the effects of sampling with a jittered clock. A novel technique based on phase demodulation of the clock oscillator and Taylor series approximation is proposed to counter the effects of clock jitter in ADCs. Since jitter is caused by phase noise, phase demodulation provides a good estimate of the instantaneous jitter. A VLSI implementation of Taylor series is used to predict the input signal value at the correct time instant.