Inserting test points to control peak power during scan testing

This paper presents a procedure for inserting test points at the outputs of scan elements of a full-scan circuit in such a manner that the peak power during scan testing is kept below a specified limit while maintaining the original fault coverage. If the power in a clock cycle during scan testing exceeds a specified limit (which depends on the peak power the chip has been designed to supply), a "peak power violation" is said to occur. Given a set of vectors, simulation is used to identify the cycles in which peak power violations occur (called "violating cycles"). For each violating cycle, the reduction in power caused by a control-0 and control-1 test point at each scan element is determined by simulation. The optimization problem then is to select as few test points as possible to eliminate all violating cycles. We present a heuristic procedure for minimizing the number of test points using integer linear programming techniques. The test points are activated and deactivated in a manner such that there is neither any loss in fault coverage nor peak power violations in the capture cycle. Experimental results indicate that the proposed procedure is very effective in controlling peak power during scan testing using a small number of test points.