Adaptable voltage scan testing of charge-sharing faults for domino circuits

Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design high-performance processors. However, domino logic suffers from several design problems and one of the most notable ones is the charge-sharing problem. Charge sharing may degrade output voltage level or even cause an erroneous output value (called charge-sharing fault). In fact, charge-sharing faults are extremely resistant to scan test, charge-sharing faults occurring at the border gates cannot be detected by any scan method, due to the missing error caused by early signal arrival time. Further, a killing error might happen in charge-sharing (CS) fault detection for both border gates and non-border gates because of the low-speed testing problem caused again by scan test. The theoretical models of these two types of CS fault are thoroughly derived. An adaptable voltage scan testing technique, which regulates the original power supply voltage (V_dd) is proposed to solve both test errors. Using a proper scan method to compromise the pre-charge situation from earlier arriving signals, and high voltage (V_dd+) to compensate the over-discharge condition from low speed clock. Finally, the test application is presented to insure the testing quality.