DocumentCode
3090569
Title
Evaluation of a software-based error detection technique by RT-level fault injection
Author
Ammari, A. ; Nicolescu, B. ; Leveugle, R. ; Savaria, Y.
Author_Institution
TIMA Lab., Grenoble, France
fYear
2006
fDate
17-19 Jan. 2006
Abstract
This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).
Keywords
fault simulation; instruction sets; microprocessor chips; transient analysis; RT-level fault injection; dependability evaluation; instruction set simulator; processor elements; programmer model; software hardening; software-based error detection; transient faults; Circuit faults; Circuit simulation; Fault detection; Flip-flops; Instruments; Logic; Programming profession; Random access memory; Registers; Robustness; dependability evaluation; fault detection; fault injection; software hardening;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Print_ISBN
0-7695-2500-8
Type
conf
DOI
10.1109/DELTA.2006.46
Filename
1581262
Link To Document