A Generation Flow for Self-Reconfiguration Controllers Customization

Partial dynamic self-reconfiguration can be obtained, in Xilinx´s Virtex families of FPGAs, through the Internal Con figuration Access Port (ICAP). Reconfiguration time is thus bounded to the ICAP rate. Different techniques have been proposed to speedup the reconfiguration process and one of the most promising one uses a memory to store the bit- stream inside the IP-Core that controls the ICAP port. The size of this memory can be chosen during the implementation phase in order to find a trade off between resource´s requirement and reconfiguration throughput. Moreover, a good level of customization can be achieved by choosing both the bus interface used by the ICAP controller and the implementation type, Slices or BRAMs, of its internal memory. This paper describes a framework used to create the most suitable controller according to the reconfiguration scenario where it will be used. To set all the parameters used to create the controller, a set of metrics, used to describe the reconfiguration scenario, has been defined. These metrics are used in the proposed flow to find the setting of the ICAP controller that best suits the scenario in which it will operate.