Test time reduction in a manufacturing environment by combining BIST and ATE

This paper analyzes an environment which utilizes Built-In Self-Test (BIST) and Automatic Test Equipment (ATE), to reduce the overall time for manufacturing test of complex digital chips. This requires properly establishing the time to switch front BIST to ATE (referred to us switchover time), thus utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment we model fault coverage us a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed: this approach is initially bused on fault simulation using a small set of random patterns: art estimate of the so-called detection profile of the circuit under test is established us basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE us related testing processes.