Development of Bit-to-Chip Block for Zigbee Transmitter on FPGA

Digital transmitter was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. However, this paper only covers the bit-to-symbol block and the symbol-to-chip block of the digital transmitter for an acknowledgment frame. These two blocks are combined together as bit-to-chip block before implemented on Spartan3E XC3S500E FPGA. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. Here, the simulation and measurement results are also presented to verify the functionality of the combined block. The frequency for input data and output data are 250 kHz and 2 MHz respectively.