A Visual Notation for Processor and Resource Scheduling

Author

Johnston, Christopher T. ; Lyons, Paul ; Bailey, Donald G.

Author_Institution

Massey Univ., Palmerston North

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

296

Lastpage

301

Abstract

Scheduling of concurrent processors in a real-time image processing system on FPGA (field programmable gate array) hardware is a not a trivial task. We propose a number of graphical representations for scheduling which were evaluated for use in a visual language for image processing on FPGAs. The proposed representations are illustrated and their strengths and weakness discussed and the reasons for adoption of the state chart notation are given.

Keywords

field programmable gate arrays; image processing; processor scheduling; real-time systems; resource allocation; visual languages; FPGA; field programmable gate array; finite state machines; graphical representations; processor scheduling; real-time image processing system; resource scheduling; state chart notation; visual language; visual notation; Automata; Electronic equipment testing; Field programmable gate arrays; Hardware design languages; Histograms; Image processing; Process control; Processor scheduling; Real time systems; System testing; FPGA; Finite state machines; Hardware design Languages; Image Processing; Visual Languages;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.76

Filename

4459560